The capacitance and capacitance sensitivity of capacitive sensing devices usually deviate from the design due to the non-ideal manufacturing and assembly process. Not only the capacitances of the components in a device may vary, but also the capacitance sensitivity of the components in the device may vary. This type of capacitance error and capacitance sensitivity error, through the amplification of the reading circuit, will be reflected to the zero-offset and the capacitance sensitivity for the overall device. Hence, the calibration method and circuit must be used to rectify the zero-offset and capacitance sensitivity back to within the specification tolerance.
Several calibration technologies for device offset are disclosed, such as, U.S. Pat. No. 5,659,262, U.S. Pat. No. 7,155,979, and U.S. Pat. No. 7,461,553. U.S. Pat. No. 5,659,262 disclosed a technology for offset trimming for a micromachined sensing device, using variable resistor to change the amplitude of input signal so as to control the voltages on the capacitor plates to achieve compensating the drift during the manufacturing process.
U.S. Pat. No. 7,155,979 and U.S. Pat. No. 7,461,533 disclosed self-calibrating oversampling electromechanical modulator and self-calibration method, for detecting the values at the equilibrium state, and calibrating the device's offset by changing the value of calibration capacitance.
A technology for calibrating shift and sensitivity of device is disclosed in U.S. Pat. No. 5,528,520. As shown in the calibration circuit of FIG. 1A and the calibration method of FIG. 1B, the calibration technology is to use two dependent digital codes of input voltages V1, V2, marked as 101, 102, and a code mirror 120 to generate four analog calibration codes. Then, the following fractional pulse density (FPD) equation is used to calibrate the zero-offset and sensitivity of the device:FPD=B+G[(CA−CB)/(CA+CB)],where zero-offset B=(½)+[VCM−(V1+V2)/2]/(V1−V2), and sensitivity G=(VDD−VCM)(V1−V2).